The present invention relates to a semiconductor testing device, and particularly to decision of PASS/FALL of a device to be tested.
FIG. 2 is a block diagram of a circuit for deciding PASS/FALL of a device to be tested in a semiconductor testing apparatus according to a prior art.
The input terminal of a driver 1 and the input terminal of a comparator 2 are connected to a device to be tested. When a testing signal is supplied to the device, the driver 1 sends an input signal to the device. When a tested signal is taken out from the device, the output from the device is supplied to the comparator 2. The output from the comparator 2 is supplied to a PASS/FAIL deciding circuit 4. The output from the PASS/FAIL deciding circuit 4 is supplied to an OR or AND circuit 5. The OR or AND circuit 5 produces a FAIL output.
There are provided a plurality of drivers 1, comparators 2 and PASS/FAIL deciding circuits 4 according to the number of terminals of the device. The output from each PASS/FAIL deciding circuit is supplied to the OR or AND circuit 5.
A testing circuit block having such a structure is individually provided for each device to be tested.
However, when the device 3 is tested by the semiconductor testing apparatus thus structured, the following problem occurs. Namely, if the device to be tested has input/output terminals whose number exceeds that of terminals of the testing circuit block, the device cannot be tested.
In this case, as shown in FIG. 3, if there is an unused testing circuit block (testing circuit block corresponding to DUTn), it can be used for testing. However, two testing circuit blocks are used to test a single device so that the number of the devices 3 to be simultaneously tested must be reduced to 1/2.